This invention relates to performing floating point arithmetic operations in programmable integrated circuit devices, such as programmable logic devices (PLDs).
As applications for which programmable devices are used increase in complexity, it has become more common to design programmable devices to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a programmable device that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on programmable devices is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, PLDs sold by Altera Corporation, of San Jose, Calif., under the family name STRATIX® include DSP blocks, each of which includes a plurality of multipliers (e.g., 18-by-18 multipliers). Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as individual multipliers, but also as smaller multipliers (by leaving some inputs unused or zeroed), or as one larger multiplier. In addition, complex multiplication (which decomposes into two multiplication operations for each of the real and imaginary parts) can be performed.
The arithmetic operations to be performed by a PLD frequently are floating point operations. The IEEE754-1985 standard requires that in floating point operations, values be normalized at all times because it implies a leading “1”.